1. Field of the Invention
The invention relates to a pseudo SRAM (PSRAM), and more particularly to a controller and a memory device of a double data rate pseudo (DDR) PSRAM, and the protocol therebetween.
2. Description of the Related Art
In portable applications, such as handheld/wireless devices, the use of low power consuming memory is essential. A PSRAM device meets both low power consumption and high density requirements. A PSRAM, like a conventional dynamic random access memory (DRAM), contains dynamic memory cells but, in terms of interface and packaging, has the appearance of a static random access memory (SRAM).
A PSRAM may operate in a burst mode. The burst mode enhances the speed of storing and retrieving data. In the burst mode, specific functions must occur in a predetermined sequence. Such functions are generally performed in response to command signals provided by a controller of the PSRAM device. The timing of the command signals is determined according a clock signal and is aligned to an edge (rising or falling) of the clock signal or occurs after a predetermined time after the edge (rising or falling) of the clock signal. Furthermore, in the burst mode, the PSRAM device may operate in fixed and variable modes of wait states, wherein the wait state determines a minimal number of clock cycles that pass before a valid data is present on a data bus.
In a double data rate (DDR) SDRAM device, both the rising and falling edges of the clock signal are trigger points for read and write operations. Compared with a single data rate (SDR) SDRAM device, the DDR SDRAM device using the same clock frequency will double the data rate, and a differential clock scheme is used to conform to increased timing accuracy requirements.